Strained-SiGe Complementary MOSFETs Adopting Different Thickness of Silicon Cap Layers for Low Power and High Performance Applications

ETRI Journal

关键词: hetero-structure MOSFET;    strained-SiGe;    strained-Si;    SiGe;   

Others  :  1185262
DOI  :  10.4218/etrij.05.0104.0148

【 摘 要 】

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility Si0.8Ge0.2 buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 μm) SixGe1-x relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) Si0.8Ge0.2 layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

   

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