A New Automatic Compensation Network for System-on-Chip Transceivers

ETRI Journal

关键词: low noise amplifier;    automatic compensation network;    System-on-chip;   

Others  :  1185565
DOI  :  10.4218/etrij.07.0106.0163

【 摘 要 】

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 m SiGe technology. This network is extremely useful for today’s radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

   

【 参考文献 】

• [1]J.-Y. Ryu and S.-H. Noh, "A New Approach for Built-In Self-Test of 4.5 to 5.5 GHz Low Noise Amplifiers," ETRI Journal, vol. 28, no. 3, June 2006, pp. 355-363.
• [2]M. Pronath, V. Gloeckel, and H. Graeb, "A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits," IEEE/ACM Int’l Conf. Computer Aided Design, Nov. 2000, pp. 557-561.
• [3]H. Liu and M. Soma, "Fault Diagnosis for Analog Integrated Circuits Based on the Circuit Layout," Proc. Pacific Rim Int’l Symp. Fault Tolerant Systems, Sep. 1991, pp. 134-139.
• [4]J. Segura, A. Keshavarzi, J. Soden, and C. Hawkins, "Parametric Failures in CMOS ICs: A Defect-Based Analysis," Proc. Int’l Test Conference, Oct. 2002, pp. 90-99.
• [5]J. Ferrario, R. Wolf, and S. Moss, "Architecting Millisecond Test Solutions for Wireless Phone RFICs," Proc. the 2003 Int’l Test Conference, Oct. 2003, pp. 1325-1332.
• [6]E.P. Vandamme, M.P. Schreurs, and C. van Dinther, "Improved Three-Step De-Embedding Method to Accurately Account for the Influence of Pad Parasitics in Silicon On-Wafer RF Test-Structures,’’ IEEE Trans. Electronic Devices, vol. 48, no. 4, Apr. 2001, pp
• [7]K.C. Craig, S.P. Case, R.E. Neese, and C.D. de Priest, "Current and Future Trusting in Automated RF and Microwave Testing," IEEE Proceedings, 1994, pp. 183-192.
• [8]F.R. de Sousa and B. Huyart, "A Reconfigurable High-Frequency Phase-Locked Loop," IEEE Trans. Instrumentation and Measurement, vol. 53, no. 4, Aug. 2004, pp. 1035-1039.
• [9]A. Chatterjee and N. Nagi, "Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial," IEEE 10th Int’l Conf. VLSI Design, Jan. 1997, pp. 388-392.
• [10]R. Voorakaranam, S. Cherubal, and A. Chatterjee, "A Signature Test Framework for Rapid Production Testing of RF Circuits," Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition, Mar. 2003, pp. 186-191.
• [11]P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analog and Design of Analog Integrated Circuits, 4th ed., New York: John Wiley & Sons, Inc., 2001.
• [12]J.Y. Ryu and B.C. Kim, "A New Design for Built-In Self-Test of 5 GHz Low Noise Amplifiers," Proc. IEEE Int’l System-On-Chip Conference, Sep. 2004, pp. 324-327.
• [13]B. Razavi, RF Microelectronics: Prentice-Hall, Inc., New Jersey, 1998, pp. 11-98.
• [14]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., New York, 2001.
• [15]J.Y. Ryu, "Built-In Self-Test for Radio Frequency System-On-Chip," PhD dissertation, Dec. 2004.
• [16]G. Girlando and G. Palmisano, "Noise Figure and Impedance Matching in RF Cascade Amplifiers," IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no. 11, Nov. 1999, pp. 1388-1396.