Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

ETRI Journal

关键词: digitally controlled oscillator (DCO);    fine-resolution;    active inductor;    wide tuning range frequency;    time amplifier;    phase-interpolator;    time-to-digital converter (TDC);    All-digital phase-locked loop (ADPLL);   

Others  :  1186105
DOI  :  10.4218/etrij.11.0110.0295

【 摘 要 】

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm2 using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is –120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

   

【 参考文献 】

• [1]R.B. Staszewski et al., "All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 12, Dec. 2005, pp. 2278-2291.
• [2]R.B. Staszewski, "TDC-Based Frequency Synthesizer for Wireless Applications," Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2004, pp. 215-218.
• [3]S. Henzler et al., "A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion," IEEE J. Solid-State Circuits, vol. 43, no. 7, July 2008, pp. 1666-1676.
• [4]Minjae Lee and A.A. Abidi, "A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue," IEEE J. Solid-State Circuits, vol. 43, no 4, Apr. 2008, pp. 769-777.
• [5]R.B. Staszewski et al., "Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process," IEEE Trans. Circuits Syst. II, vol. 50, no. 11, Nov. 2003, pp. 815-828.
• [6]D. Leenaerts et al., "A SiGe BiCMOS 1 ns Fast Hopping Frequency Synthesizer for UWB Radio," Proc. IEEE Int. Solid-State Circuits Conf. Dig., vol. 1, Feb. 2005, pp. 202-593.
• [7]YoungGun Pu et al., "Wide-Band Fine-Resolution DCO with an Active Inductor and Three-Step Coarse Tunning Loop," ETRI J., vol. 33, no. 2, Apr. 2011, pp. 201-209.
• [8]V. Kratyuk et al., "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy," IEEE Trans. Circ. Syst. II, vol. 54, no. 3, Mar. 2007, pp. 247-251.
• [9]S.K. Mitra, Digital Signal Processing: A Computer-Based Approach, New York: McGraw-Hill, 2001.
• [10]Third Generation Partnership Project, "Technical Specification Group Radio Access Network," User Equipment Radio Transmission and Reception (Rel. 8), 3GPP TS 36.101 V8.5.1.
• [11]P. Dudek, S. Szczepanski, and J.V. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line," IEEE J. Solid-State Circuits, vol. 35, no. 2, Feb. 2000, pp. 240-247.
• [12]C.-M. Hsu, M.Z. Straayer, and M.H. Perrott, "A Low-Noise, Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," IEEE J. Solid-State Circuits, vol. 43, no. 12, Dec. 2008, pp. 2776-2786.
• [13]V. Kratyuk et al., "A Digital PLL with a Stochastic Time-to-Digital Converter," IEEE Trans. Circuits Syst. I, vol. 56, no. 8, Aug. 2009, pp. 1612-1621.