Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach

ETRI Journal

关键词: quasi-floating gate;    CMOS voltage follower;    CMOS buffer;    Analog integrated circuits;   

Others  :  1186108
DOI  :  10.4218/etrij.11.0110.0465

【 摘 要 】

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW).

   

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