期刊论文详细信息
ETRI Journal
New Multiplier for a Double-Base Number System Linked to a Flash ADC
关键词: flash ADC;    double-base number encoder;    DBNS;   
Others  :  1186408
DOI  :  10.4218/etrij.12.0211.0198
PDF
【 摘 要 】

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

【 授权许可】

   

【 预 览 】
附件列表
Files Size Format View
20150520125424373.pdf 338KB PDF download
【 参考文献 】
  • [1]R. Kacem et al., "Low Power Implementation of Digital Filters Using DBNS Representation and Sub-expression Sharing," 2nd Int. Conf. Signals, Circuits, Syst., Nov. 2008, pp. 1-6.
  • [2]S.-C. Huang and L.-G. Chen, "A 32-Bit Logarithmic Number System Processor," J. VLSI Signal Process., vol. 14, no. 3, 1996, pp. 311-319.
  • [3]V.S. Dimitrov, G.A. Jullien, and W.C. Miller, "Theory and Applications of the Double-Base Number System," IEEE Trans. Comput., vol. 48, no. 10, 1999, pp. 1098-1106.
  • [4]V.S. Dimitrov and G.A. Jullien, "Loading the Bases: A New Number Representation with Applications," IEEE Circuits Syst. Mag., vol. 3, no. 2, 2003, pp. 6-23.
  • [5]I. Kim et al., "Highly Efficient Comparator Design Automation for TIO Flash A/D Converter," IEICE Trans. Fundamentals of Electron. Commun. Comput. Sci., vol. E91-A, no. 12, Dec. 2008.
  • [6]J. Lim et al., "Low Power Flash A/D Converter with TIQ Comparators for Multi-standard Mobile Applications," IREE, vol. 4, Dec. 2009, pp. 1447-1452.
  • [7]M.S. Nguyen et al., "Algorithm and Design of Double-Base Log Encoder for Flash A/D Converter," KISPS, vol. 10, no. 4, Oct. 2009, pp. 289-293.
  • [8]H.-J. Kang and I.-C. Park, "FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders," IEEE Trans. Circuits Syst., vol. 48, Aug. 2001, pp. 770-778.
  • [9]S. Paul, N. Jayakumar, and S.P. Khatri, "A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations," IEEE Trans. VLSI Syst., vol. 17, no. 2, Feb. 2009, pp. 269-277.
  • [10]M. Gok, "A Novel IEEE Rounding Algorithm for High-Speed Floating-Point Multipliers," VLSI J., vol. 40, no. 4, 2007, pp. 549-560.
  文献评价指标  
  下载次数:5次 浏览次数:8次