Parallel computations on pedigree data through mapping to configurable computing devices

Genetics Selection Evolution

Bryce Alvin Little¹  John M Henshall¹ 

[1] FD McMaster Laboratory Chiswick, CSIRO Livestock Industries, Armidale, New South Wales 2350, Australia

关键词: pedigree data;    parallel computations;    FPGA;   

Others  :  1094126
DOI  :  10.1186/1297-9686-38-3-265

 received in 2005-08-16, accepted in 2005-11-18,  发布年份 2006

【 摘 要 】

Pedigree data structures have a number of applications in genetics, including the estimation of allelic or haplotype probabilities in humans and agricultural species, and the estimation of breeding values in agricultural species. Sequential algorithms for general purpose CPU-based computers are commonly used, but are inadequate for some tasks on large data sets. We show that pedigree data can be directly represented on Field Programmable Gate Arrays (FPGA), allowing highly efficient massively parallel simulation of the flow of genes. Operating on the whole pedigree in parallel, the transmission of genes can occur for all individuals in a single clock cycle. By using FPGA, the algorithms to estimate inbreeding coefficients and allelic probabilities are shown to operate hundreds to thousands of times faster than the corresponding sequentially based algorithms. Where problems can be largely represented in an integer form, FPGA provide an efficient platform for computations on pedigree data.

【 授权许可】

   
2006 INRA, EDP Sciences