VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

International Research and Innovation Summit 2017

Ahmad, Nabihah^1 ; Mokhtar, Ahmad Hakimi^1 ; Othman, Nurmiza Binti^1 ; Soon, Chin Fhong^1 ; Rahman, Ab Al Hadi Ab^2

Nano Simulation Research Group (NanoSIM), Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Johor, Batu Pahat

86400, Malaysia^1

Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Johor, Johor Bahru

81310, Malaysia^2

关键词: Electronic design automation tools;    Fault-tolerance capability;    Low-power consumption;    Metal oxide semiconductors (CMOS);    Multiplier architecture;    Propagation delays;    Reversible logic gates;    VLSI implementation;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/226/1/012140/pdf
DOI  :  10.1088/1757-899X/226/1/012140

来源: IOP

【 摘 要 】

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.