Research on SEU hardening of heterogeneous Dual-Core SoC

2nd Annual International Conference on Information System and Artificial Intelligence

物理学;计算机科学

Huang, Kun^1 ; Hu, Keliu^1 ; Deng, Jun^1 ; Zhang, Tao^1

Sichuan Institute of Solid-State Circuits, China Electronics Technology Group Corp, Chongqing

400060, China^1

关键词: Dual core;    Financial resources;    Hamming code;    Low costs;    Random access memory;    Single event upsets;    Triple modular redundancies (TMR);   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/887/1/012022/pdf
DOI  :  10.1088/1742-6596/887/1/012022

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

The implementation of Single-Event Upsets (SEU) hardening has various schemes. However, some of them require a lot of human, material and financial resources. This paper proposes an easy scheme on SEU hardening for Heterogeneous Dual-core SoC (HD SoC) which contains three techniques. First, the automatic Triple Modular Redundancy (TMR) technique is adopted to harden the register heaps of the processor and the instruction-fetching module. Second, Hamming codes are used to harden the random access memory (RAM). Last, a software signature technique is applied to check the programs which are running on CPU. The scheme need not to consume additional resources, and has little influence on the performance of CPU. These technologies are very mature, easy to implement and needs low cost. According to the simulation result, the scheme can satisfy the basic demand of SEU-hardening.