Fabricating with crystalline Si to improve superconducting detector performance

12th International Workshop on Low Temperature Electronics

Beyer, A.D.^1 ; Hollister, M.I.^2 ; Sayers, J.^2 ; Frez, C.F.^1 ; Day, P.K.^1 ; Golwala, S.R.^2

Jet Propulsion Laboratory, California Institute of Technology, Pasadena

CA, United States^1

California Institute of Technology, Pasadena

CA, United States^2

关键词: Amorphous dielectrics;    Coplanar wave-guide (CPW);    Crystalline Si (c-Si);    Deep reactive ion etch;    Parallel plate capacitors;    Silicon on insulator wafers;    Superconducting detector;    Wafer bonding process;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/834/1/012006/pdf
DOI  :  10.1088/1742-6596/834/1/012006

来源: IOP

【 摘 要 】

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F• δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F• δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.