A low jitter all - digital phase - locked loop in 180 nm CMOS technology

International Conference on Particle Physics and Astrophysics

Shumkin, O.V.^1 ; Butuzov, V.A.^1 ; Normanov, D.D.^1 ; Ivanov, P. Yu^1

National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Kashirskoe highway 31, Moscow

115409, Russia^1

关键词: All digital phase locked loop;    CMOS technology;    Digital phase locked loops;    Digitally controlled oscillators;    Low jitters;    Operating condition;    System on Chip application;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/675/4/042042/pdf
DOI  :  10.1088/1742-6596/675/4/042042

来源: IOP

【 摘 要 】

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.