Evaluating the power efficiency and performance of multi-core platforms using HEP workloads

21st International Conference on Computing in High Energy and Nuclear Physics

物理学;计算机科学

Szostek, P.^1 ; Innocente, V.^1

CERN, Geneva

CH-1211, Switzerland^1

关键词: Complex architectures;    Instruction set;    Multi-core platforms;    Power efficiency;    Processor design;    Shared memory;    Silicon industry;    Transistor count;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/664/9/092024/pdf
DOI  :  10.1088/1742-6596/664/9/092024

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

As Moore's Law drives the silicon industry towards higher transistor counts, processor designs are becoming more and more complex. The area of development includes core count, execution ports, vector units, uncore architecture and finally instruction sets. This increasing complexity leads us to a place where access to the shared memory is the major limiting factor, resulting in feeding the cores with data a real challenge. On the other hand, the significant focus on power efficiency paves the way for power-aware computing and less complex architectures to data centers. In this paper we try to examine these trends and present results of our experiments with Haswell-EP processor family and highly scalable HEP workloads.