Use of checkpoint-restart for complex HEP software on traditional architectures and Intel MIC

15th International Workshop on Advanced Computing and Analysis Techniques in Physics Research

物理学;计算机科学

Arya, Kapil^1 ; Cooperman, Gene^1 ; Dotti, Andrea^2 ; Elmer, Peter^3

College of Computer and Information Science, Northeastern University, Boston, MA, United States^1

SLAC National Accelerator Laboratory, Menlo Park, CA 94025, United States^2

Department of Physics, Princeton University, Princeton, NJ 08540, United States^3

关键词: Check pointing;    Efficient scheduling;    High-level triggers;    Many-core computing;    Multi- threaded applications;    Scalability and performance;    Single-threaded;    Traditional architecture;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/523/1/012015/pdf
DOI  :  10.1088/1742-6596/523/1/012015

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

Process checkpoint-restart is a technology with great potential for use in HEP workflows. Use cases include debugging, reducing the startup time of applications both in offline batch jobs and the High Level Trigger, permitting job preemption in environments where spare CPU cycles are being used opportunistically and efficient scheduling of a mix of multicore and single-threaded jobs. We report on tests of checkpoint-restart technology using CMS software, Geant4-MT (multi-threaded Geant4), and the DMTCP (Distributed Multithreaded Checkpointing) package. We analyze both single- and multi-threaded applications and test on both standard Intel x86 architectures and on Intel MIC. The tests with multi-threaded applications on Intel MIC are used to consider scalability and performance. These are considered an indicator of what the future may hold for many-core computing.