A PCIe Gen3 based readout for the LHCb upgrade

20th International Conference on Computing in High Energy and Nuclear Physics

物理学;计算机科学

Bellato, M.^1 ; Collazuol, G.^4 ; D'Antone, I.^3 ; Durante, P.^2 ; Galli, D.^5 ; Jost, B.^2 ; Lax, I.^3 ; Liu, G.^2 ; Marconi, U.^3 ; Neufeld, N.^2 ; Schwemmer, R.^2 ; Vagnoni, V.^3

INFN Sezione di Padova, Italy^1

CERN European Centre for Nuclear Research, Switzerland^2

INFN Sezione di Bologna, Italy^3

Università di Padova, INFN Sezione di Padova, Italy^4

Università di Bologna, INFN Sezione di Bologna, Italy^5

关键词: Alternative solutions;    Baseline design;    Bunch crossings;    Cost effective;    Data acquisition system;    Events triggers;    Front end electronics;    High-level triggers;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/513/1/012023/pdf
DOI  :  10.1088/1742-6596/513/1/012023

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

The architecture of the data acquisition system foreseen for the LHCb upgrade, to be installed by 2018, is devised to readout events trigger-less, synchronously with the LHC bunch crossing rate at 40 MHz. Within this approach the readout boards act as a bridge between the front-end electronics and the High Level Trigger (HLT) computing farm. The baseline design for the LHCb readout is an ATCA board requiring dedicated crates. A local area standard network protocol is implemented in the on-board FPGAs to read out the data. The alternative solution proposed here consists in building the readout boards as PCIe peripherals of the event-builder servers. The main architectural advantage is that protocol and link-technology of the event-builder can be left open until very late, to profit from the most cost-effective industry technology available at the time of the LHC LS2.