NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

20th International Conference on Computing in High Energy and Nuclear Physics

物理学;计算机科学

Ammendola, Roberto^1 ; Biagioni, Andrea^2 ; Fantechi, Riccardo^3,4 ; Frezza, Ottorino^2 ; Lamanna, Gianluca^4 ; Lo Cicero, Francesca^2 ; Lonardo, Alessandro^2 ; Paolucci, Pier Stanislao^2 ; Pantaleo, Felice^4,5 ; Piandani, Roberto^4 ; Pontisso, Luca^6 ; Rossetti, Davide^2 ; Simula, Francesco^2 ; Sozzi, Marco^4,5 ; Tosoratto, Laura^2 ; Vicini, Piero^2

INFN, Rome-Tor Vergata, Italy^1

INFN, Rome-Sapienza, Italy^2

CERN, Geneve, Switzerland^3

INFN, Pisa, Italy^4

Universiy, Pisa, Italy^5

University, Rome, Italy^6

关键词: Input datas;    Integrated systems;    Low latency;    Readout boards;    Real time;    Synthetic benchmark;    Trigger systems;    UDP protocol;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/513/1/012018/pdf
DOI  :  10.1088/1742-6596/513/1/012018

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.