Many-core applications to online track reconstruction in HEP experiments

20th International Conference on Computing in High Energy and Nuclear Physics

物理学;计算机科学

Amerio, S.^1 ; Bastieri, D.^1 ; Corvo, M.^1 ; Gianelle, A.^1 ; Ketchum, W.^2 ; Liu, T.^3 ; Lonardo, A.^4 ; Lucchesi, D.^1 ; Poprocki, S.^5 ; Rivera, R.^3 ; Tosoratto, L.^4 ; Vicini, P.^4 ; Wittich, P.^5

INFN, University of Padova, Padova, Italy^1

Los Alamos National Laboratory, Los Alamos

NM, United States^2

Fermi National Accelerator Laboratory, Batavia

IL, United States^3

INFN Roma, Rome, Italy^4

Cornell University, Ithaca

NY, United States^5

关键词: Computing architecture;    Graphic processing units (GPUs);    High energy physics experiments (HEP);    Many integrated core architecture (MIC);    Parallel devices;    Performance measurements;    Serial algorithms;    Track reconstruction;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/513/1/012002/pdf
DOI  :  10.1088/1742-6596/513/1/012002

学科分类：计算机科学（综合）

来源: IOP

【 摘 要 】

Interest in parallel architectures applied to real time selections is growing in High Energy Physics (HEP) experiments. In this paper we describe performance measurements of Graphic Processing Units (GPUs) and Intel Many Integrated Core architecture (MIC) when applied to a typical HEP online task: the selection of events based on the trajectories of charged particles. We use as benchmark a scaled-up version of the algorithm used at CDF experiment at Tevatron for online track reconstruction-the SVT algorithm-as a realistic test-case for low-latency trigger systems using new computing architectures for LHC experiment. We examine the complexity/performance trade-off in porting existing serial algorithms to many-core devices. Measurements of both data processing and data transfer latency are shown, considering different I/O strategies to/from the parallel devices.