Best voltage bias-flipping strategy towards maximum piezoelectric power generation

13th International Conference on Micro and Nanotechnology for Power Generation and Energy Conversion Applications

物理学;能源学

Liang, Junrui^1 ; Chung, Henry Shu-Hung^2

School of Information Science and Technology, ShanghaiTech University, 319 Yueyang Road, Shanghai 200031, China^1

Centre for Smart Energy Conversion and Utilization Research, City University of Hong Kong, Kowloon Tong, Hong Kong^2

关键词: Energy optimization;    Extracted energies;    Interface circuits;    Piezo-electric structures;    Piezoelectric energy harvesting;    Piezoelectric power;    Piezoelectric voltage;    Vibration velocity;   

Others  :  https://iopscience.iop.org/article/10.1088/1742-6596/476/1/012025/pdf
DOI  :  10.1088/1742-6596/476/1/012025

来源: IOP

【 摘 要 】

In piezoelectric energy harvesting (PEH) systems, energy extracted from piezoelectric structure can be increased by making piezoelectric voltage in phase with vibration velocity and raising the voltage amplitude. Such voltage manipulations can be realized by synchronously flipping the piezoelectric voltage with respect to a bias dc source at every displacement extremum. Given that net harvested energy is obtained by deducting dissipated energy from total extracted energy, a sophisticated voltage bias-flipping scheme, which can maximize extracted energy at low dissipative cost, is required towards harvested energy optimization. This paper extends the state of the art by proposing the best bias-flip strategy, which is delivered on conceptual synchronized multiple bias-flip (SMBF) interface circuits. The proposed strategy coordinates both requirements on larger voltage change in synchronized instant for more extracted energy and smaller voltage change in each bias-flip action for less dissipated energy. It not only leads to further enhancement of harvesting capability beyond existing solutions, but also provides an unprecedented physical insight on maximum achievable harvesting capability of PEH interface circuit.