Parametric and topological methods of bulk CMOS IP-blocks yield improvement

2nd International Telecommunication Conference "Advanced Micro- and Nanoelectronic Systems and Technologies"

Gerasimov, Y.M.^1 ; Grigoryev, N.G.^1 ; Kobylyatskiy, A.V.^1

National Research Nuclear University MEPhI, Moscow Engineering Physics Insitutute, Kashirskoe shosse 31, Moscow

115409, Russia^1

关键词: Bulk CMOS;    Nanometer VLSI;    Topological methods;    Yield Improvement;    Yield loss;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/498/1/012024/pdf
DOI  :  10.1088/1757-899X/498/1/012024

来源: IOP

【 摘 要 】

This paper presents the study of the main reasons for the yield loss of modern nanometer VLSIs. The methods of the yield improvement are described on the basis of the impact of parametric and catastrophic reasons for its loss.