Dynamically Reconfigurable Architectures Dagstuhl Seminar 10281 Proceedings Abstract

Dynamically Reconfigurable Architectures

计算机科学;物理学;数学

P. Athanas ; J. Becker, J. Teich ; I. Verbauwhede

Others  :  http://drops.dagstuhl.de/opus/volltexte/2010/2892/pdf/10281.SWM.ExtAbstract.2892.pdf
PID  :  44970

学科分类：计算机科学（综合）

来源: CEUR

【 摘 要 】

Dynamic and partial reconfiguration of hardware architectures such as FPGAs and coarse grain processing arrays bring an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. When compared to emerging software-programmable Multi-Processor System-on-a-Chip (MPSoC) solutions, they benefit a lot from lower cost, more dedication and fit to a certain problem class as well as power and area efficiency. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamiccontrol, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity. [First Paragraph]