Advances and Trends in Dynamic Partial Run-time Reconfiguration

Dynamically Reconfigurable Architectures

计算机科学;物理学;数学

Dirk Koch ; Jim TΦrresen

Others  :  http://drops.dagstuhl.de/opus/volltexte/2010/2841/pdf/10281.KochDirk.Paper.2841.pdf
PID  :  44969

学科分类：计算机科学（综合）

来源: CEUR

【 摘 要 】

Partial runtime reconfiguration allows to fit circuits on an FPGA that would exceed the device capacity in a static only implementation. This implementation technique is only applicable if the system contains modules with mutual exclusive functionality or if the utilization of some modules allow time-multiplexing of the same FPGA resources. For example, as illustrated in Figure 1, in an FPGA-based network package inspection hardware, the same device resources (a reserved reconfigurable area on the FPGA) can be used for hosting different accelerator modules. Then, during runtime, this system can adapt to the current protocol load of the network traffic. As the total load is limited by the network itself, the variation among different protocols will lead to different demands among the corresponding accelerators. As one example, the different demands could been served by instantiating more or less accelerator instances.