Multiple Event Upsets Aware FPGAs Using Protected Schemes

Fault-Tolerant Distributed Algorithms on VLSI Chips

计算机科学;物理学

Costas Argyrides ; Dhiraj K. Pradhan

PID  :  79800

学科分类：计算机科学（综合）

来源: CEUR

【 摘 要 】

Multiple upsets would be available in SRAMbased FPGAswhich utilizes SRAM in different parts to implement circuit configuration and to implement circuit data. Moreover, configuration bits of SRAM based FPGAs are more sensitive to upsets compared to circuit data due to significant number of SRAM bits. In this paper, a new protected Con figurable Logic Block (CLB) and FPGA architecture are proposed which utilize multiple error correction (DEC) and multiple error detection. This is achieved by the incorporation of recently proposed coding technique Matrix codes [1] inside the FPGA. The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.